In operation, the memory plane of a non-volatile memory may be subject to short-circuits, for example between a bit line and the control gate of the memory cell connected to this bit line, owing to the breakdown of an insulator, for example an insulating spacer situated on the flanks of the control gate.
This may then result in defects in this bit line which is then considered as damaged or faulty, and whose content, in other words the contents of the memory cells connected to this bit line, is then considered as lost.
In other words, when the bits contained in these locations are read, these defective memory locations lead to erroneous logical values.
One conventional solution consists in using an error correction code (or ECC) in order to correct the erroneous logical value of a bit. More precisely, with an error correction code, if s control bits are added to b data bits r errors from amongst the b+s bits can be corrected.
Generally speaking, the error correction codes used in the field of memories allow only one error (r=1) to be corrected within the word of b+s bits.
However, the defective nature of a bit line will compromise the capacity for correction of the ECC mechanism because the error in a word due to one damaged bit from a defective bit line risks being added to another error in another bit of this word then leading to a double error in the word which is indeed detected but not corrected.